I recently obtained some of Microchips new Serial SRAMS (Static Random Access Memories) and had a chance to have a play with them a little while ago and a couple of interesting things popped up.

I’ve gotten hold of the 2.7 to 3.6 volt, PDIP variants (but they are also available in 1.5 to 1.95 volts and in SOIC and TSSOP packages), and this means that interfacing them to a PIC running at 5 volts isn’t all plain sailing so I've created a seperate Tech-Tip that covers some possible ways you can “glue” components together when they are running at different incompatible voltages.

The datasheet for these wee beasties isn’t a tome, and so is straight forward to read and understand.

Now if your used to using more traditional parallel access memories like the 61512 SRAM’s, older technology EPROMS and everything in between, then you will be quite at home with the concept of the Chip Select and that fact that if you’ve only got one device on the bus, you can tie it to an appropriate logic level and save yourself some address decoding logic or an I/O pin.
Now even though SPI is usually flouted as a 3-wire bus (Data In, Data Out and Clock), it often needs 4 wires and these Serial SRAMS are no exception as to complete the read or write cycles for these memories, you have to control the Chip Select; that is unless you are reading or writing the Status register when it doesn’t seem to matter. This actually caught me out and had me scratching my head for 30 minutes. If you read the datasheet carefully, it’s in there, clear as day.

One other thing to note is standards and naming conventions. If you want to use a PIC’s hardware MSSP module to control SPI memories, you have to use certain PIC pins that are connected internally to the MSSP. On my datasheet for the 18F2550 these pins are labelled SDO (Serial Data Out), SDI (Serial Data In) and SCK (Serial Data Clock); all perfectly straight forward.

The datasheet for the Serial SRAM’s calls the pins SO (Serial Data Output), SI (Serial Data Input) and SCK (Serial Clock Input). Whilst it’s no big issue, it would be nice if a standard naming convention could be adopted across the range. It would certainly be less confusing for people who are new to the technology.

I mentioned before about using the MSSP module and if possible this should be the preferred way to go, at least with these memories as this will gice you the fastest performance for the smallest code side. But remember that the MSSP works with 8bits to the byte which is fine for these devices, but some devices may require data that’s not a multiple of 8 bits, and so you may have problems interfacing in these cases. Always read the datasheet… twice.

So, after a slight detour to build in some voltage translation and to then control the memories Chip Select correctly, I had my new memories working correctly.

...there just memories after all.
Well, memories come in either Serial or Parallel flavours, and each have their own associated merit.

Serial memories typically require only a few control signals but tend to be a bit slower than traditional parallel memories that in turn require many control signals to interface to them. If memory access speed isn’t too much of a problem then serial memories can be a good choice as it reduces the overall design complexity but there may be another problem. Until recently, most serial memories were EEPROM technology (Electronically Erasable Programmable Read Only Memory) and as such, they were often rather slow and had a finite life when it came to write cycles. They are great for storage of static date or data results from sensors and the like as EEPROM technology is classed as NVR (Non Volatile RAM) and won’t lose its contents when the power is turned off; ideal for battery powered devices. But you could not for example, use an EEPROM for the main RAM in a computer as even a modest CPU running at a few MHz would damage the EEPROM after a short time constantly reading and writing the same locations. It’s like pacing up and down on the same bit of carpet; eventually you wear a hole in it where as standard RAM would take this type of abuse in its stride.

The Microchip SRAMS give have the benefits of a simple electrical interface of 4 signals, and the read/write endurance of standard RAM. Their only downside is that because they are serial access, they are slower than traditional parallel RAM’s but when you consider that they have a maximum clock speed of around 20MHz you will probably find them fast enough for all but the most demanding applications.